• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    According to the present invention, a bias is applied to the body portion of the main transistor, thereby lowering the threshold voltage at the transition of a logic value so that a rapid operation is performed, and otherwise, a high leakage voltage is maintained to maintain a high threshold voltage. The purpose of the present invention is to provide a field effect transistor capable of operating without limit to the operating voltage. According to the present invention, there is provided a semiconductor device comprising: a first transistor formed in a body portion of a semiconductor and having a source, a drain, a channel portion formed between the source and a drain, and a gate connected to the channel portion; A second transistor formed in a body portion of the semiconductor, the second transistor having a source, a drain, a channel portion formed between the source and the drain, and a gate connected to the channel portion; The source of the second transistor is connected to the body portion of the first transistor, the drain of the second transistor is connected to the gate of the first transistor, the gate of the second transistor is the drain or source of the first transistor. Provided is a semiconductor device characterized in that it is connected to.
    公开号:KR19990074292A
    申请号:KR1019980007771
    申请日:1998-03-09
    公开日:1999-10-05
    发明作者:신형철；길준호；제민규；이종호
    申请人:윤덕용；한국과학기술원；
    IPC主号:
    专利说明:

    High Speed / Low Power Field Effect Transistors with Auxiliary Transistors
    The present invention relates to a high speed / low power field effect transistor (FET) having a subsidiary MOSFET. More particularly, the source of the sub transistor is connected to the body portion of the main transistor. In addition, the gate of the auxiliary transistor is connected to the source or drain of the main transistor to bias the body portion of the main transistor, thereby lowering the threshold voltage at the transition of the logic value. The present invention relates to a field effect transistor that enables fast operation and otherwise maintains a high threshold voltage to reduce leakage current.
    Recently, digital logic circuits have been developed for high speed and low power operation. In particular, as most electronic products are portable, the demand for low power is gradually increasing.
    In order to configure a logic circuit that operates at low power, a low operating voltage may be provided. However, in this case, the operation speed of the logic circuit is significantly reduced. In general, to operate a MOSFET requires about three times the operating voltage of the threshold voltage.
    1 is a circuit diagram of a conventional field effect transistor (FET) for low power for this purpose, which is presented in US Pat. No. 5,559,368.
    A field effect transistor is formed in a body region of a semiconductor and includes a source, a drain, a channel region between the source and the drain, and a gate connected on the channel region. (gate).
    The logic circuit of the conventional field effect transistor for lowering power, as shown in US Patent No. 5,559, 368, connects the source of the second transistor 12 to the body portion of the first transistor 11, as shown in FIG. The drain of the second transistor 12 is connected to the gate of the first transistor 11, and the source of the first transistor 11 is connected to the reference potential Vdd. The gate of the second transistor 12 is connected to an appropriate gate voltage to bias the gate. As a result, the second transistor 12 provides a forward bias to the body portion of the first transistor 11 associated with the source of the first transistor 11.
    Since the conventional field effect transistor applies a predetermined voltage to the gate of the auxiliary transistor, a basic operating voltage (about 0.7 V) is required in a logic circuit employing such a transistor structure. Therefore, such a logic circuit has a problem in that an operating voltage is limited and the circuit becomes complicated when it is applied to the logic circuit.
    Accordingly, the present invention has been made to solve the above problems of the prior art, the present invention is to connect the source of the auxiliary transistor to the body portion of the main transistor, the gate of the auxiliary transistor or By connecting to the drain and biasing the body of the main transistor, the threshold voltage at the transition of the logic value is lowered so that the fast operation is performed, and otherwise, the high threshold voltage is maintained. It is an object of the present invention to provide a field effect transistor which allows the leakage current to be small and operates without limiting the operating voltage.
    1 is a circuit diagram of a conventional field effect transistor (FET).
    Figure 2a is a circuit diagram of an N-type field effect transistor according to an embodiment of the present invention.
    2B is a circuit diagram of a P-type field effect transistor according to an embodiment of the present invention.
    3 is a circuit diagram of an inverter to which the present invention is applied.
    Figure 4a is a graph comparing the input and output state of the inverter to which the present invention is applied with a conventional output.
    Figure 4b is a graph showing the potential change of the body portion of the main transistor according to the present invention.
    * Description of the symbols for the main parts of the drawings *
    21: primary n-type transistor 22: auxiliary n-type transistor
    23: main P-type transistor 24: auxiliary P-type transistor
    Therefore, according to the present invention for achieving the above object, a first transistor formed in the body portion of the semiconductor, and having a source, a drain, a channel portion formed between the source and the drain, and a gate connected to the channel portion Wow; A second transistor formed in a body portion of the semiconductor, the second transistor having a source, a drain, a channel portion formed between the source and the drain, and a gate connected to the channel portion; The source of the second transistor is connected to the body portion of the first transistor, the drain of the second transistor is connected to the gate of the first transistor, the gate of the second transistor is the drain or source of the first transistor. Provided is a semiconductor device characterized in that it is connected to.
    In the following, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    FIG. 2A is a circuit diagram of an N-type field effect transistor according to an embodiment of the present invention, where 21 is a main N-type transistor and 22 is an auxiliary N-type transistor.
    As shown in FIG. 2A, in the present invention, two general metal oxide semiconductor (MOS) transistors are provided, one of which operates as a main transistor 21, and the other as an auxiliary transistor 22. It is used as a means for applying a bias to the body portion of the main transistor 22.
    Looking at the connection relationship between the auxiliary transistor 22 and the main transistor 21, the source of the auxiliary transistor 22 is connected to the body portion of the main transistor 21. The drain of the auxiliary transistor 22 is connected to the gate of the main transistor 21, and the gate of the auxiliary transistor 22 is connected to the drain or source of the main transistor 21.
    Here, the present invention connects the gate of the auxiliary transistor 22 to the source or drain of the main transistor 21, as compared with the aforementioned conventional U.S. Patent No. 5,559,368, which is why the present invention limits the operating voltage. The circuit configuration is simple and can be easily implemented when applied to logic circuits.
    FIG. 2B is a circuit diagram of a P-type field effect transistor according to an embodiment of the present invention, where 23 is a main P-type transistor and 24 is an auxiliary P-type transistor.
    Like the N-type transistor described in FIG. 2A, the P-type transistor shown in FIG. 2B also includes an auxiliary transistor 24 and a main transistor 23, and has the same connection structure.
    In the following, the transistor circuit of the present invention as described above will be applied to a specific logic circuit and its operation and effects will be described.
    FIG. 3 is a circuit diagram of an inverter to which the present invention is applied, and FIG. 4a is a graph comparing input and output states of the inverter to which the present invention is applied with a conventional output. A graph showing potential change.
    In the inverter circuit shown in Fig. 3, the P-type auxiliary transistor Mp * is connected to the P-type main transistor Mp as shown in the present invention only in a general inverter circuit, and the N-type auxiliary transistor is connected to the N-type main transistor Mn. (Mn * ) has a connected configuration.
    That is, the drain of the P-type auxiliary transistor Mp * is connected to the gate of the P-type main transistor Mp connected to the input terminal, and the source of the P-type auxiliary transistor Mp * is the body portion of the P-type main transistor Mp. The gate of the P-type auxiliary transistor Mp * is connected to the drain of the P-type main transistor Mp connected to the output terminal. Meanwhile, the drain of the N-type auxiliary transistor Mn * is connected to the gate of the N-type main transistor Mn connected to the input terminal, and the source of the N-type auxiliary transistor Mn * is the body portion of the N-type main transistor Mn. The gate of the N-type auxiliary transistor Mn * is connected to the source of the N-type main transistor Mn connected to the output terminal.
    Looking at the operation of the inverter circuit having such a configuration as follows.
    First, look at the operation when the input value transitions from '0' to '1'. If the input value is '0', the P-type main transistor Mp is turned on to form a channel, so the output value is '1'. Becomes In this case, since the gate of the N-type auxiliary transistor Mn * is connected to the output terminal, the N-type auxiliary transistor Mn * is turned on, and the P-type auxiliary transistor Mp * and the N-type main transistor Mn are turned on. -Off. In this case, therefore, the body portion of the N-type main transistor Mn becomes '0'.
    Now, when the input value changes from '0' to '1', the P-type main transistor Mp is turned off, and the N-type main transistor Mn is turned on, so that the N-type main transistor Mn and the N-type auxiliary transistor are turned on. The transistors Mn * are all turned on. As a result, the input value '1' is transmitted to the body portion of the N-type main transistor Mn through the formed channel of the N-type auxiliary transistor Mn * , so that the body voltage of the N-type main transistor Mn is turned on in the diode. -The voltage rises rapidly to about 0.7 volts. As a result, the threshold voltage of the N-type main transistor Mn is lowered, the current of the N-type main transistor Mn is increased, and the load capacitor C L of the output terminal is discharged more quickly. As the output gradually drops to '0', the body voltage of the N-type main transistor (Mn) decreases due to the inflow of the auxiliary transistor channel electrons and the capacitive-coupling effect. After the logic transition, the body voltage of the N-type main transistor Mn is about 0 to 0.3 volts. Through this process, as the output terminal transitions to '0', the N-type auxiliary transistor Mn * is turned off and the P-type auxiliary transistor Mp * is turned on.
    When the input value changes from '1' to '0', the body voltage of the N-type main transistor Mn becomes '0', and the P-type main transistor Mp is turned on. In this case, since both the P-type main transistor Mp and the P-type auxiliary transistor Mp * are turned on, an input value of '0' is applied to the body of the P-type main transistor Mp. Therefore, since the turn-on voltage of the P-type main transistor Mp rises rapidly, the threshold voltage is lowered. As a result, the output stage is quickly affected by the reference potential Vdd.
    Graphs showing the results of these operations are shown in FIGS. 4A and 4B. As described above, the present invention can be applied not only to the inverter circuit described above but also to a logic circuit in the form of a complementary pass-transistor logic (CPL) or complementary symmetry MOS (CMOS).
    As shown in FIGS. 4A and 4B, the threshold voltage is lowered by applying a bias to the body of the main transistor, so that the operation is faster than the conventional operation result as shown in FIG. 4A.
    Therefore, the present invention configured as described above enables low voltage and high speed operation, can be used without limitation to the operating voltage, and the circuit structure is simple, so that the overall chip area can be reduced when the present invention is applied to a logic circuit. .
    Although the technical idea of the high speed / low power field effect transistor having the auxiliary transistor of the present invention has been described with the accompanying drawings, the present invention has been described by way of example and is not intended to limit the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.
    权利要求:
    Claims (2)
    [1" claim-type="Currently amended] A first transistor formed in a body portion of the semiconductor and having a source, a drain, a channel portion formed between the source and the drain, and a gate connected to the channel portion;
    A second transistor formed in a body portion of the semiconductor, the second transistor having a source, a drain, a channel portion formed between the source and the drain, and a gate connected to the channel portion;
    The source of the second transistor is connected to the body portion of the first transistor, the drain of the second transistor is connected to the gate of the first transistor, the gate of the second transistor is connected to the drain of the first transistor A semiconductor device, characterized in that.
    [2" claim-type="Currently amended] A first transistor formed in a body portion of the semiconductor and having a source, a drain, a channel portion formed between the source and the drain, and a gate connected to the channel portion;
    A second transistor formed in a body portion of the semiconductor, the second transistor having a source, a drain, a channel portion formed between the source and the drain, and a gate connected to the channel portion;
    The source of the second transistor is connected to the body portion of the first transistor, the drain of the second transistor is connected to the gate of the first transistor, the gate of the second transistor is connected to the source of the first transistor. A semiconductor device, characterized in that.
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    同族专利:
    公开号 | 公开日
    KR100271207B1|2000-11-01|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-03-09|Application filed by 윤덕용, 한국과학기술원
    1998-03-09|Priority to KR1019980007771A
    1999-10-05|Publication of KR19990074292A
    2000-11-01|Application granted
    2000-11-01|Publication of KR100271207B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980007771A|KR100271207B1|1998-03-09|1998-03-09|High speed and low electric power fet with subsidiary mosfet|
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